Metal lines formed over a semiconductor wafer typically require a protective capping layer to prevent oxidation. One conventional approach to providing such protection utilizes a dielectric capping layer. Another approach utilizes a metal capping layer because of its stronger adherence to the metal lines it covers. Formation of a metal capping layer on metal lines requires use of a selective deposition process to avoid shorting between the lines caused by an accumulation of the metal capping layer between the metal lines. However, because existing methods for selective deposition are not entirely selective, their use may still result in some accumulation of metal capping material between the metal lines.
Although the deficiencies associated with the approaches to providing a protective capping layer for metal lines alluded to above are manageable for larger line dimensions and interlineal spacing, as circuits move to ever smaller dimensions, those deficiencies become more critical. In the case of dielectric capping layers, which exhibit lower metal line adhesion than metal capping layers, the higher current densities resulting from narrower lines may result in impermissibly high levels of electromigration along the dielectric capping layer/metal line interface. Use of a metal capping layer, on the other hand, avoids this electromigration problem. However, at higher line densities, the accumulation of capping material between lines produced by conventional selective deposition processes can cause shorting between adjacent metal lines and can degrade the reliability of the integrated circuit.